Software & Architectural Techniques for Cache Leakage Reduction in Nanometer-scale Embedded Systems

Опубликовано 6 сентября 2016, 17:12

Energy consumption is a fundamental barrier in taking full advantage of integration capability of today and future semiconductor manufacturing technology. With technology scaling to nanometer dimensions, leakage (static) power is gaining a bigger share in total power consumption, and furthermore, variation is increasing in transistor parameters (such as gate length, width, and threshold voltage, V_th ) such that leakage as well as delay varies even among SRAM cells located within the same die. We present our recent research activities and results on reducing cache leakage energy under real-time constraints in processor-based embedded systems. This includes /(i)/ reducing leakage energy in instruction cache by taking advantage of value-dependence of SRAM leakage due to within-die V_th variation, /(ii)/ using asymmetric SRAM designs that leak less when storing a 0, and then renaming register-operands of instructions so as to increase number of zeros in instruction-cache, and hence, to reduce leakage,/ (iii)/ shifting the delay-distribution curve of SRAM cells toward higher delays without impacting delay, capacity, or timing-yield of the entire cache by adding extra cache-ways or by adding spare rows/columns of SRAM. We also briefly review our other works in Kyushu University on estimating and reducing static and dynamic power consumption of real-time embedded systems and also overview our methodology developed in Sharif University of Technology for efficient hardware-software implementation of object-oriented embedded applications