Using the DDS & FIR Compiler IPs with the AMD Kria KD240 Drives Starter Kit

Опубликовано 3 сентября 2024, 16:56

Welcome to the "Using the DDS & FIR Compiler IPs with the AMD Kria KD240 Drives Starter Kit" demonstration.

We'll start with an overview of the AMD Kria KD240 Drives Starter Kit and the basics of DDS and FIR compiler IPs. Next, we’ll explain the design flow process, including block design creation and validation, bitstream generation, and exporting the XSA from the AMD Vivado Design Suite. Then, we’ll show you how to create a Vitis platform using the exported XSA and how to program the programmable logic with the bitstream. Finally, we’ll show how to access the ILA from the Hardware Manager of the Vivado IDE.

The AMD Kria KD240 Drives Starter Kit is an evaluation platform for the K24 SOM focused on motor control and power conversion applications. The KD240 and its base K24 SOM support full user customization through the AMD Vitis Unified IDE, customizable acceleration overlays, and AMD Vivado Design Suite hardware board files.

The AMD Vivado Integrated Design Environment offers an intuitive graphical user interface for visualizing and interacting with FPGA designs. The design used in this demo will utilize two specific IP blocks from the Vivado IP catalog: the DDS Compiler IP and the FIR Compiler IP. The AMD DDS Compiler IP creates a customizable direct digital synthesizer. A DDS uses a look-up table for sine wave values. It takes a phase increment as input and outputs the corresponding sine wave data point. With regards to the AMD FIR Compiler IP, it is a configurable FIR filter that allows a user to simply specify the filter coefficients and hardware parameters, such as coefficient width and sampling frequency.

References: hackster.io/whitney-knitter/ds...

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