Optimize Memory and Cache Usage with Intel® VTune™ Profiler | Intel Software

Опубликовано 4 мая 2023, 16:43

This video demonstrates using Intel VTune Profiler memory access analysis and micro-architecture analysis to identify a memory access bottleneck and improve performance by optimizing use of memory cache.
Hotspot analysis with hardware event-based analysis is used to pinpoint an application performance bottleneck associated with a memory access.

More detailed analysis is then used to identify opportunities for reducing the number of L3 cache accesses and thus increase performance.

In this video we demonstrate the use of the Intel VTune Profiler in conjunction with other Intel® oneAPI Base Toolkit components like the Intel® oneAPI DPC++/C++ Compiler. It provides a hands-on example of the benefits of using VTune Profiler to optimize application performance. In this specific scenario we look at memory and cache accesses. Hotspot Analysis identifies a DRAM memory access taking many clock ticks. Further micro-architecture analysis points to cache misses and L3 cache accesses. The resolution is the use of built-in compiler prefetch commands to improve data access times.
In addition to hotspot analysis, we go over various views the VTune Profiler provides to aid with your analysis:
• The platform diagram shows DRAM bus utilization
• The bandwidth utilization histogram reports memory accesses of varying bandwidth
• The latency histogram shows memory accesses and their latency and allows to identify their origin.
This dataset then allows us to identify the remedy and reduce high latency cache usage.

Intel® VTune™ Profiler: intel.com/content/www/us/en/de...

Intel Distribution for Python*: intel.com/content/www/us/en/de...

Intel® oneAPI: intel.com/content/www/us/en/de...

oneAPI Code Samples Library: intel.com/content/www/us/en/de...

oneAPI Code Samples Catalog: oneapi-src.github.io/oneAPI-sa...

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Optimize Memory and Cache Usage with Intel® VTune™ Profiler | Intel Software