CMPLE - Melting the Ice Between Cores

Опубликовано 6 сентября 2016, 6:31

Chip Multiprocessors (CMPs) have emerged as the common choice for processor manufacturers to take advantage of CMOS scaling trends that lead to greater numbers of smaller transistors on a single chip. CMP architectures feature multiple simple cores that help mitigate wire delays and energy consumption issues facing complex monolithic designs. However, with the exception of server applications such as database programs, the majority of commonly used applications on desktop machines have yet to heed the transition in processors and become multithreaded. The result of running single-threaded programs on a CMP is overall processor utilization levels only at a fraction of its full potential. While various Thread-level parallelism (TLP) approaches such as speculative multithreading, helper threads, and activity migration, each feature unique capabilities that can improve an aspect of single-threaded programs running on CMPs, each one requires a different type of connectivity among the cores to achieve its goal. In addition, each application benefits from a different set of techniques and a universal CMP architecture needs to support all of them at the same time. Consequently, current CMP designs are inadequate for building a universal computation framework because they are too rigid. In this talk, we present a robust CMP architecture featuring more diverse and numerous connection capabilities to provide a universal substrate that can efficiently implement existing paradigms while paving the way for novel future TLP models. Referred to as CMP with Linked Execution or CMPLE (pronounced simple) in short, this architecture tailors the appearance of the processor to better match the application requirements by providing a generic microarchitectural connectivity substrate for different cores to communicate. With the potential help of helper threads, different cores on the CMPLE architecture cooperate in executing a single-threaded program in order to improve its performance, security, and reliability.