Helping Moore's Law: Architectural Techniques to Address Parameter Variation

Опубликовано 6 сентября 2016, 17:23

Advances in microprocessor technology have driven growth in the computing industry for decades. However, as transistors reach deep-nanometer scales, manufacturing challenges are causing increased variability in transistor characteristics. This in turn is contributing to slower processor frequency increases, higher power consumption and decreased reliability. Unless remedial action is taken, it is estimated that the gains of an entire technology generation may be lost. In this talk I will present two techniques I developed to address this problem at the microarchitecture and system levels. The first technique is based on fine-grain body biasing, in which different regions of a multicore chip are given different bias voltages that change the speed and power consumption of their transistors. I proposed dynamic fine-grain body biasing, which allows continuous adjustment of the bias voltages to adapt to changes in temperature or workload. The result is a reduction in variation, improving frequency and reducing power consumption. The second technique is based on variation-aware algorithms for application scheduling and power management in multicore chips. These algorithms use information about the frequency and power characteristics of each core to optimize application scheduling and to adjust the voltage and frequency settings for each core. This technique is very effective at saving power and improving performance of multicore chips affected by variation.